处理器供电要求

Power Supply Requirements

电源管脚

最小电压(V)

典型电压(V)

最大电压(V)

最大电流(mA)

详细描述

PVDD

2.97

3.3

3.63

150

PVDD system power input, connected to a 10uF capacitor

BUCK_LX

-

1.25

-

50

BUCK output pin, connected to a 4.7uH inductor

BUCK_FB

-

1.25

-

50

BUCK feedback and internal power input pin, connected to the other end of the inductor and an external 4.7uF capacitor

VDD_VOUT1

-

1.1

-

50

Internal LDO, with an external 4.7uF capacitor

VDD_VOUT2

-

0.9

-

20

Internal LDO, with an external 4.7uF capacitor

VDD_RET

-

0.9

-

1

Internal LDO, with an external 0.47uF capacitor

VDD_RTC

-

1.1

-

1

Internal LDO, with an external 1uF capacitor

VDDIOA

1.71

1.8/3.3

3.63

-

GPIO power input, with an external 1uF capacitor

AVDD33

2.97

3.3

3.63

100

3.3V analog power input, with an external 4.7uF capacitor

AVDD33_AUD

2.97

3.3

3.63

50

3.3V audio power input, with an external 2.2uF capacitor

VDD_SIP

1.71

1.8/3.3

3.63

30

Internal LDO, or external power input(1) ，外接1uF电容

AVDD_BRF

2.97

3.3

3.63

100

Analog power input, with an external 4.7uF capacitor

MIC_BIAS

1.4

-

2.8

-

MIC power output, with an external 1uF capacitor

Note

(1)

  • SF32LB52BU36 requires an external supply of 1.8V or 3.3V

  • SF32LB52BU56 requires an external supply of 3.3V

  • For SF32LB52E/G/JUx6, when PVDD=1.8V, the internal LDO cannot be used and an external 1.8V supply is needed when PVDD=3.3V, the internal LDO supplies power directly, no external supply needed

Important

When the system is in Hibernate mode, VDD_SIP power supply should be turned off, otherwise there is a risk of leakage on the I/O of the encapsulated storage。Please use the dedicated PA21 pin for the VDD_SIP power control signal。